data sheet 26186.122 8-bit addressable dmos power driver the A6B259ka and A6B259klw combine a 3-to-8 line cmos decoder and accompanying data latches, control circuitry, and dmos outputs in a multi-functional power driver capable of storing single-line data in the addressable latches or use as a decoder or demuliplexer. driver applications include relays, solenoids, and other medium- current or high-voltage peripheral power loads. the cmos inputs and latches allow direct interfacing with micro- processor-based systems. use with ttl may require appropriate pull- up resistors to ensure an input logic high. four modes of operation are selectable with the clear and enable inputs. the A6B259ka/klw dmos open-drain outputs are capable of sinking up to 500 ma. similar devices with reduced r ds(on) are avail- able as the a6259ka/klw. the A6B259ka is furnished in a 20-pin dual in-line plastic package. the A6B259klw is furnished in a 20-lead wide-body, small-outline plastic package (soic) with gull-wing leads for surface- mount applications. copper lead frames, reduced supply current requirements, and low on-state resistance allow either device to sink 150 ma from all outputs continuously, to ambient temperatures greater than 85 c. features 50 v minimum output clamp voltage 150 ma output current (all outputs simultaneously) 5 ? typical r ds(on) low power consumption replacements for tpic6b259n and tpic6b259dw 6b259 advance information (subject to change without notice) january 24, 2000 always order by complete part number: part number package r ja r jc A6B259ka 20-pin dip 55 c/w 25 c/w A6B259klw 20-lead soic 70 c/w 17 c/w logic ground 1 2 3 8 9 13 14 15 16 17 19 4 5 6 7 12 18 20 data s (lsb) logic supply v dd power ground clear out 7 out 6 out 5 dwg. pp-050-1 out 0 out 1 out 2 out 3 out 4 10 11 no (internal) connection no (internal) connection nc nc enable en power ground latches decoder logic latches 0 s 1 s (msb) 2 note that the A6B259ka (dip) and the A6B259klw (soic) are electrically identical and share a common terminal number assignment. absolute maximum ratings at t a = 25 c output voltage, v o ............................... 50 v output drain current, continuous, i o .......................... 150 ma * peak, i om ................................... 500 ma? single-pulse avalanche energy, e as ................................................. 30 mj logic supply voltage, v dd .................. 7.0 v input voltage range, v i ................................... -0.3 v to +7.0 v package power dissipation, p d ........................................... see graph operating temperature range, t a ................................. -40 c to +125 c storage temperature range, t s ................................. -55 c to +150 c * each output, all outputs on. ? pulse duration 100 s, duty cycle 2%. caution: these cmos devices have input static protection (class 3) but are still susceptible to damage if exposed to extremely high static electrical charges.
6b259 8-bit addressable dmos power driver 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 w copyright ?2000, allegro microsystems, inc. function table inputs addressed other clear enable data output outputs function hlh l r addressable hll h r latch h h x r r memory llh l h 8-line lll h h demultiplexer l h x h h clear l = low logic level h = high logic level x = irrelevant r = previous state latch selection table select inputs addressed s 2 ( msb )s 1 s 0 ( lsb ) output lll 0 llh 1 lhl 2 lhh 3 hll 4 hlh 5 hhl 6 hhh 7 logic symbol g8 z9 9,0d 10,0r 4 5 6 7 14 15 16 17 8 12 18 13 dw g . fp-046 0 2 3 19 z10 8m 0/7 9,1d 10,1r 9,2d 10,2r 9,3d 10,3r 9,4d 10,4r 9,5d 10,5r 9,6d 10,6r 9,7d 10,7r 50 75 100 125 150 2.5 0.5 0 allowable package power dissipation in watts ambient temperature in c 2.0 1.5 1.0 25 dwg. gs-004a suffix 'lw', r = 70 c/w ja suffix 'a', r = 55 c/w ja dmos power driver output logic inputs in dwg. ep-010-15 v dd dwg. ep-063 out
6b259 8-bit addressable dmos power driver www.allegromicro.com grounds (terminals 9, 10, and 11) must be connected externally to a single point. ground dwg. fp-047 data clear (active low) enable (active low) v dd logic supply out 0 d c1 clr out 1 d c1 clr out 2 d c1 clr out 3 d c1 clr out 4 d c1 clr out 5 d c1 clr out 6 d c1 clr out 7 d c1 clr 2 s (msb) 1 s 0 s (lsb) functional block diagram
6b259 8-bit addressable dmos power driver 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 limits characteristic symbol test conditions min. typ. max. units logic supply voltage v dd operating 4.5 5.0 5.5 v output breakdown v (br)dsx i o = 1 ma 50 v voltage off-state output i dsx v o = 40 v, v dd = 5.5 v 0.1 5.0 a current v o = 40 v, v dd = 5.5 v, t a = 125 c 0.15 8.0 a static drain-source r ds(on) i o = 100 ma, v dd = 4.5 v 4.2 5.7 ? on-state resistance i o = 100 ma, v dd = 4.5 v, t a = 125 c 6.8 9.5 ? i o = 350 ma, v dd = 4.5 v (see note) 5.5 8.0 ? nominal output i on v ds(on) = 0.5 v, t a = 85 c90ma current logic input current i ih v i = v dd = 5.5 v 1.0 a i il v i = 0, v dd = 5.5 v -1.0 a prop. delay time t plh i o = 100 ma, c l = 30 pf 150 ns t phl i o = 100 ma, c l = 30 pf 90 ns output rise time t r i o = 100 ma, c l = 30 pf 200 ns output fall time t f i o = 100 ma, c l = 30 pf 200 ns supply current i dd(off) v dd = 5.5 v, outputs off 20 100 a i dd(on) v dd = 5.5 v, outputs on 150 300 a typical data is at v dd = 5 v and is for design information only. note ?pulse test, duration 100 s, duty cycle 2%. electrical characteristics at t a = +25 c, v dd = 5 v, t ir = t if 10 ns (unless otherwise specified). recommended operating conditions over operating temperature range logic supply voltage range, v dd ............... 4.5 v to 5.5 v high-level input voltage, v ih ............................ 0.85v dd low-level input voltage, v il ................................. 0.15v dd
6b259 8-bit addressable dmos power driver www.allegromicro.com functional description and input requirements four modes of operation are selectable by controlling the clear and enable inputs as shown above. in the addressable-latch mode, data at the data input is written into the addressed transparent latch. the addressed output inverts the data input with all other outputs remaining in their previous states. in the memory mode, all outputs remain in their previous states and are unaffected by the data or address (s n ) inputs. to prevent entering erroneus data in the latches, enable should be held high while the address lines are changing. in the demultiplexing/decoding mode, the addressed output inverts the data input and all other outputs are off. in the clear mode, all outputs are off and are unaf- fected by the data or address (s n ) inputs. given the appropriate inputs, when data is low for a given address, the output is off; when data is high, the output is on and can sink current. data input requirements data active time before enable (data set-up time), t su(d) .............................................. 20 ns data active time after enable (data hold time), t h(d) ................................................... 20 ns data pulse width, t w(d) ....................................................... 40 ns input logic high, v ih ................................................ 0.85v cc input logic low, v il ................................................. 0.15v cc 50% dwg. wp-037 enable data 50% w(d) t su(d) t h(d) t phl t plh t 50% addressed output dwg. wp-036 10% 90% f t r t enable data output switching time
6b259 8-bit addressable dmos power driver 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 test circuits single-pulse avalanche energy test circuit and waveforms e as = i as x v (br)dsx x t av /2 10.5 ? +15 v out 200 mh dut dwg. ep-066 input i o v o t av i as = 500 ma v (br)dsx v o(on)
6b259 8-bit addressable dmos power driver www.allegromicro.com terminal descriptions terminal no. terminal name function 1 nc no (internal) connection. 2 logic supply (v dd ) the logic supply voltage (typically 5 v). 3s 0 binary-coded output-select input, least-significant bit. 4 out 0 current-sinking, open-drain dmos output, address 000. 5 out 1 current-sinking, open-drain dmos output, address 001. 6 out 2 current-sinking, open-drain dmos output, address 010. 7 out 3 current-sinking, open-drain dmos output, address 011. 8s 1 binary-coded output-select input. 9 logic ground reference terminal for logic voltage measurements. 10 power ground reference terminal for output voltage measurements (out 0-3 ). 11 power ground reference terminal for output voltage measurements (out 4-7 ). 12 s 2 binary-coded output-select input, most-significant bit. 13 enable mode control input; see function table. 14 out 4 current-sinking, open-drain dmos output, address 100. 15 out 5 current-sinking, open-drain dmos output, address 101. 16 out 6 current-sinking, open-drain dmos output, address 110. 17 out 7 current-sinking, open-drain dmos output, address 111. 18 data cmos data input to the addressed output latch. when enabled, the addressed output inverts the data input (data = high, output = low). 19 clear mode control input; see function table. 20 nc no (internal) connection. note ?grounds (terminals 9, 10, and 11) must be connected externally to a single point.
6b259 8-bit addressable dmos power driver 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 A6B259ka dimensions in inches (controlling dimensions) dimensions in millimeters (for reference only) notes: 1. exact body and lead configuration at vendor? option within limits shown. 2. lead spacing tolerance is non-cumulative. 3. lead thickness is measured at seating plane or below. 0.014 0.008 0.300 bsc dwg. ma-001-20 in 0.430 max 20 1 10 0.280 0.240 0.210 max 0.070 0.045 0.015 min 0.022 0.014 0.100 bsc 0.005 min 0.150 0.115 11 1.060 0.980 0.355 0.204 7.62 bsc dwg. ma-001-20 mm 10.92 max 20 1 10 7.11 6.10 5.33 max 1.77 1.15 0.39 min 0.558 0.356 2.54 bsc 0.13 min 3.81 2.93 11 26.92 24.89
6b259 8-bit addressable dmos power driver www.allegromicro.com A6B259klw dimensions in inches (for reference only) dimensions in millimeters (controlling dimensions) 0 to 8 1 2 3 0.020 0.013 0.0040 min. 0.0125 0.0091 0.050 0.016 dwg. ma-008-20 in 0.050 bsc 20 11 0.2992 0.2914 0.419 0.394 0.5118 0.4961 0.0926 0.1043 0 to 8 1 20 2 3 0.51 0.33 0.10 min. dwg. ma-008-20 mm 1.27 bsc 11 0.32 0.23 1.27 0.40 7.60 7.40 10.65 10.00 13.00 12.60 2.65 2.35 notes: 1. exact body and lead configuration at vendor s option within limits shown. 2. lead spacing tolerance is non-cumulative.
6b259 8-bit addressable dmos power driver 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 the products described here are manufactured under one or more u.s. patents or u.s. patents pending. allegro microsystems, inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. the information included herein is believed to be accurate and reliable. however, allegro microsystems, inc. assumes no responsi- bility for its use; nor for any infringement of patents or other rights of third parties which may result from its use.
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